The present invention relates to high performance general purpose digital computer systems, and more particularly, to a system that permits detailed trouble shooting of such a general purpose computer system without impeding the performance thereof.
The three main units of a basic general purpose digital computer system are the central processing unit (CPU), the memory, and the input-output (I/O) units. In order to achieve high performance parallel computational power, super computers and mini-supercomputers utilize multiple interactive CPUs, pipeline architectures and array processors.
Digital codes carrying information inside a general purpose computer system must be communicated between the various units. The multiple wires that form the physical conduits for these digital codes are referred to as buses. Each of the I/O units of a computer system is given an address and each information location in the memory is given an address. To locate specific information in the memory, a digital code, namely the address of the information, is sent on an address bus to the memory by the CPU. At the same time other digital codes representing control signals are sent on a control bus to tell the memory either to read or to write the information from the memory location designated by the address on the address bus. The actual information coming to the CPU from the memory when the memory is read, or going to the memory from the CPU when the information is to be written, is also in the form of digital codes traveling along a data bus. Collectively these address, control and data buses may be referred to as a system bus.
In communicating information along the buses, it is conventional to employ a parity bit in the digital codes as a way of helping to detect single bit errors that may occur during transmission. The parity is determined by counting the number of ones in the byte or character code. If the number of ones is an odd number, and even parity is desired, then the parity bit is set to one so that there is an even total number of ones. If, on the other hand, odd parity is desired, and the word is the same as in the previous example, then a zero is selected for the parity bit so that there is an odd total number of ones. The parity generating circuit in the transmitting unit counts the number of ones in the code to be sent and sets the parity bit as required. The receiving unit also counts the number of ones and determines what the parity bit should be. Then it compares the received parity bit to the determined parity bit. If the parity bits match, then it is assumed that no error has occurred in the data transmission. On the other hand, if the parity bits do not match, then it is assumed that an error has occurred in the data transmission and appropriate action is taken. It will be understood that parity does not ensure that all errors in data transmission will be detected. For example, if an even number of ones were lost in the transmission, then the number of ones would still be odd or even, as it was before the transmission. However, the use of a parity bit provides a simple and convenient way of testing for errors that may occur in the course of data transmission inside the computer.
In conventional general purpose digital computer systems each module that sends data generates the parity bit and each module that receives data checks the parity. Thus each module has to have both parity generating and parity checking capabilities, which results in an unnecessary duplication of hardware within the computer.
Larger general purpose computer systems, e.g. mini, main frame, mini super and super computers, typically have some diagnostic or troubleshooting capabilities. In some instances, it is desirable to perform detailed troubleshooting by examining the actual bits and bytes of information communicated along the busses. Preferably such troubleshooting should not prevent or otherwise impede the normal operation of the computer so that users can continue using the system. It would be desirable to provide a system that could perform these diagnostic and parity checking functions with improved flexibility in regard to examining the digital signals transmitted along the system bus of a high performance digital computer.